Using GPT and POEG for Waveform Generation (IrDA)
Renesas RA MCUs come with the General PWM Timer (GPT) peripheral for output waveform generation. By configuring the timer settings of the GPT, it is possible to create periodic waveforms. RA devices also have the Port Output Enable for GPT (POEG) peripheral that further enhances this ability by allowing additional triggers to control when the GPT output is enabled or disabled.
To demonstrate this, the following example shows how an IrDA signal can be both generated and interpreted by an MCU that does not have IrDA PHY hardware included. Using the GPT and POEG peripherals along with the Event Link Controller (ELC), this can be done without any intervention from the CPU, reducing processor overhead.
The accompanying example project can be found at the end of this article.
IrDA Format vs. UART
IrDA is a serial standard for communicating with infrared transceivers. It behaves similarly to a UART interface, with some key differences.
The first difference is that the high/low bit states are reversed in IrDA: a '1’ in UART format is represented by a LOW data line in IrDA, and a ‘0’ in UART becomes a HIGH line.
The other key difference in IrDA is that the HIGH data states do not take up the full bit width. They are represented by a pulse with a width that is 3/16 of the bit period. The image below shows a frame of data represented in both UART and IrDA format.
We can use the MCU’s SCI UART to send and receive data, and the GPT and POEG modules can handle translation to and from the IrDA format.
Hardware Setup
This example uses the EK-RA2E1 board with some additional pin connections made with the available pin headers. It uses a total of six MCU pins: SCI Tx and Rx, two GPT outputs, and two POEG inputs. The following table shows which specific pins are used, and which pins should be shorted.
| Output Pin | Pin Function | Input Pin | Pin Function |
Pin Connections | P205 | SCI0 Tx | P401 | GTETRGA |
P213 | GTIOC0A | P104
| GTETRGB
| |
P111 | GTIOC6A | P206 | SCI0 Rx |
Software Setup
The FSP is used to configure each peripheral to ensure that the waveform translation works properly. The required stacks are shown below.
Configure POEG0
As previously mentioned, POEG0’s input pin GTETRGA is connected to the UART’s Tx pin to capture rising and falling edges. The FSP stack is configured as shown below.
For this application, General > Trigger > GTETRG Pin is checked, General > Channel is set to 0, and General > Input > GTETRG Polarity is set to Active High. These settings configure POEG0 for trigger detection on GTETRGA.
Configure the IrDA Encode Timer GPT Module
These are the FSP configuration options for the GPT module used as the IrDA encoding timer, with the key options highlighted by the red boxes:
First, Pin Output Support must be Enabled so that the GPT output pin can be used.
In the General section, Mode is set to Saw-wave PWM, Period is set to 115200, and Period Unit is set to Hertz. The period setting of 115200 Hertz was chosen because that is the UART baud rate used in this example. With these settings, the timer will overflow with a timing equal to that of a single UART bit transmission.
Under Output > Custom Waveform > GTIOA, the settings are as follows:
Initial Output Level – Pin Level Low
Cycle End Output Level – Pin Level Low
Compare Match Output Level – Pin Level Toggle
Retain Output Level at Count Stop – Disabled
Because the HIGH pulses on the IrDA data do not take up the entire bit period, the data line needs to be LOW for most of the transmission. With these settings, the GPT output will always remain low unless a timer compare match occurs.
One tier below, in the Output > Custom Waveform section, Custom Waveform Enable is set to Enabled to allow the waveform to be generated.
Another tier up, in Output:
Duty Cycle Percent – 81
GTIOCA Output Enabled – True
GTIOCA Stop Level – Pin Level Low
Because the IrDA pulse width is 3/16 of the bit width, and 3/16 ≈ 19%, the output will start low at the start of a timer cycle and remain there for the first 81% of the bit period. It will then go high for the final 3/16 of the period. The other options ensure that the specific output pin GTIOCA is used and is LOW when the timer is stopped.
In Input > Start Source, the box for GTETRGA Falling Edge is checked.
In Input > Stop Source, GTETRGA Rising Edge is checked.
These settings determine the timer start/stop behavior, and they are dependent on edge detection of the POEG input. Since the SCI0 Tx line is connected to this input, the timer will start when the Tx line goes LOW and will stop when the Tx line goes HIGH. The waveform capture below shows an example of data output marked when this timer module starts and stops. The green waveform is the UART Tx line which is fed to GTETRGA pin. The yellow waveform is the resulting output from the GPT.
You can see the GPT output remains low for nearly the entire timer period but then goes high to indicate the ‘0’ bit on the UART. Once the timer stops or expires, the GPT output returns to the low state.
Configure POEG1
To capture and decode the IrDA waveform, the output of the GPT module from the previous sections needs to be tied to the POEG1 GTETRG pin. The FSP settings are the same as those for POEG0, except for the Channel field being set to 1.
Configure the IrDA Decode Timer GPT Module
A second GPT output needs to be configured to convert the newly generated IrDA waveform to a UART-format one. This timer module will be configured similarly to the encode timer, but there are some differences.
To start, Pin Output Support must be Enabled.
In the General section, Mode is set to Periodic, Period is set to 115200, and Period Unit is set to Hertz. We are not using the duty cycle feature for this one, so Periodic mode is acceptable.
Under Output > Custom Waveform > GTIOA, the settings are as follows:
Initial Output Level – Pin Level Low
Cycle End Output Level – Pin Level Low
Compare Match Output Level – Pin Level Retain
Retain Output Level at Count Stop – Disabled
Most of these are the same as in the other module; however, Pin Level Retain is used because we want the timer output to remain at its current level when the timer expires.
To enable the output pin for the module, set GTIOCA Output Enabled to True. Set the GTIOCA Stop Level to Pin Level High so that the generated UART signal will idle high.
In Input > Start Source, the box for GTETRGB Falling Edge is checked.
In Input > Stop Source, GPT6 COUNTER OVERFLOW (Overflow) is checked. These settings will cause the timer to start once a falling edge is detected on the input waveform, and the timer will stop once the timer overflows after the full bit period has elapsed.
These settings will result in a waveform that idles high and goes low when the POEG input detects a falling edge. If the incoming signal has sequential high pulses, the timer will reset, and the output will remain low. Only when the timer expires will the output return to high.
The figure below shows the output UART waveform generated from the IrDA input waveform. You can see the UART output initially goes low when the timer starts, and once the timer expires (triggering the timer Stop condition), the output returns to the high state.
Encoding and Decoding Example
The below image shows the three relevant data signals in a single image.
Here we have the following waveforms:
Green — The original UART output
Yellow — The IrDA waveform generated by the GPT, encoded from the green signal
Blue — The UART output waveform generated by the other GPT, decoded from the yellow signal
You can see that the resulting blue waveform is identical to the original green waveform for the purpose of reading UART data.
The attached example configures and initializes the peripherals as described in this document. Making the necessary pin connections as shown in the Hardware Setup section will allow the application to function properly.
After initializing the relevant peripherals, the program loops a sequence of UART write and read, with a delay in-between.